【15】CS61C Midterm 2 Cheatsheet

  1. Setup Time, Hold Time, CLK-to-Q

  2. 1554879464158

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  3. To convert a truth table to a boolean expression, use sum-of-products and then simplify.

  4. Critical Path: Max Delay = CLK-to-Q Delay + CL Delay + Setup Time

  5. Hold Time Requirement: $t_{clk-to-q} + t_{logic, shortest} > t_{hold}$

  6. 5 Phases of execution: IF, ID, EX, MEM, WB

  7. 1554881187636

  8. Pipelining Increases throughput, increases clock frequency, But can never improve latency, sometimes worse.

  9. Hazards: Structural (A required resource is busy), Data (Data dependency between instructions), Control hazard (Flow of execution depends on previous instruction)

  10. Structural: Add more hardware (separate instruction/data memories, RegFile multiple ports, double pumping)

  11. Data: Forwarding (lw: one cycle stall, re-ordering)

  12. Control: branch prediction, flush if incorrect

  13. Locality: Temporal, Spatial.

  14. Cache fields: Tag | Index | Offset, Size of Index = log2 (number of sets)

  15. Direct Mapped(N=1), N-way Set Associative, Fully Associative(N=block#)

  16. Write Policy: Hit: Write-Through, Write-Back(write when evict, dirty bit); Miss: no write allocate, write allocate

  17. AMAT = Time for a hit + Miss rate × Miss penalty

  18. Sources of Misses: Compulsory, Capacity, Conflict, Coherence

  19. Floating point number: sign, exponent(8, 11), fraction(23, 52), $(-1)^s * (1 + F) * 2^E$

  20. 1554927296452

  21. Latency (Time/Task) and Bandwidth (Tasks/Time)


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2019-04-11 06:00 +0800

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